Hello everyone, and happy Eid! This week, while I have yet to make much progress on implementation, I wanted to dive deeper into a problem we discussed last time: full activation. This issue revolves around identifying which primary inputs and values should be assigned to activate a fault in a digital design. Let's explore this problem and the proposed solution in detail.
The problem begins when we have a design, read it, pass it, and identify a fault from the fault file. The challenge is to determine which primary inputs and what values they should have to activate the fault. For instance, consider an AND gate in the middle of a design with a stuck-at-1 fault. To activate this fault, we need the AND gate's output to be zero, achievable only if at least one of its inputs is zero. Hence, we must propagate a zero value from some primary input to the AND gate, contradicting the fault's value.
The complexity arises due to the numerous possibilities and permutations of input values affecting each gate's outputs. The goal is to trace the signal back to the primary inputs to determine the necessary values.
The solution, inspired by the video lecture provided below, involves backtracing the signal from the fault site to the primary inputs. This method requires calculating the inversion parity while propagating the signal back. For example, if three inverters exist between the AND gate and the nearest primary input, the inversion parity would be three. The signal needed at the primary input depends on the inversion parity and the target fault output.
To implement this, I referred to a GitHub repository, which influenced my approach to backtracing. The implementation iterates over the inputs of the target gate (the gate with the fault) and traces a path to a primary input. It then calculates the inversion parity, sets the value at the primary input, and checks if it activates the fault. If not, it explores another path.
https://www.youtube.com/watch?v=Dm3dP-6TMyk
A crucial aspect of fault activation involves understanding controlling and non-controlling input values for logic gates.
Controlling values are inputs that can determine the output of a gate regardless of other inputs. For example:
To detect a fault in a gate with controlling values, we need to force the gate's output to a value that contradicts the fault. For instance, if an AND gate has a stuck-at-0 fault, we need the output to be 1, which requires all inputs to be 1.
Non-controlling values do not determine the output by themselves; the output depends on all inputs. For example: